Capacitors are implemented within integrated circuits for a number of reasons, including coupling the power supply voltage line (e.g., bus) and the ground line (bus) to reduce voltage noise by locally meeting charge requirements for current-switching circuits. This capacitive coupling between the power supply voltage line and the ground line is known as supply bypassing. Such on-chip capacitors are typically implemented with active transistors, connected as gate capacitors, and often are implemented wherever there is space on the silicon die, between other functional circuits. That is, due to the placement of circuits, or floorplanning, within the die, there may be some regions where a small number of capacitors may be implemented because there was less need for other circuitry in that area. Conversely, there may be regions where there was no room to implement capacitors.
Gate capacitors have two commonly known issues in their use as effective integrated circuit capacitors. First, the resistance of a salicided poly gate is typically an order of magnitude higher than on-chip metal. This adds a series resistance to the gate capacitor, which reduces the quality-factor of the capacitor, thus reducing the capacitor's effectiveness. Secondly, there is a reliability restriction of connecting gate capacitors with oxide thicknesses of less than 20 Angstroms directly to a power supply line due to gate reliability concerns during an electrostatic discharge (i.e., ESD) event. Gate capacitors with larger oxide thicknesses can be directly connected, but they have much lower capacitance per unit area than gate capacitors with smaller gate thicknesses.
In many instances the physical location of the on-chip capacitors are a relatively large distance from where the stored charge is required. This distance results in a voltage droop due to the impedance of the power line when the capacitor energy is applied to the switching circuit. The higher the frequency of the switching circuit, the more the voltage droop can become, since the stored charge on the voltage line cannot keep up with the re-charge requirements between circuit switches. This voltage droop is a voltage noise on the power line which may cause degradation in circuit performance.
For example, an integrated circuit die may be 10 mm×10 mm, and have the on-chip supply coupling capacitors implemented in only one quadrant of the die, therefore easily being many millimeters from current-switching circuits requiring the capacitive charge.
Typically, integrated circuits provide some inherent capacitance due to the implementation of the metal power mesh (grid). FIG. 1 illustrates an exemplary power mesh of an integrated circuit in accordance with the prior art. As shown in FIG. 1, power mesh 100 shows two metal layers 105 and 110 of an integrated circuit, for example, though a typical power mesh may be comprised of several metallization layers. The layers 105 and 110 are electrically isolated from one another by dielectric layer 115. As shown in FIG. 1, the lower metallization layer includes alternating ground wires 106 (i.e., Vss) and voltage wires 107 (i.e., Vdd) which are shown running horizontally across the lower metallization layer, electrically isolated from each other by dielectric 108.
The upper-metal layer 110, which overlies the lower-metal layer 105, likewise, includes alternating ground wires 111 and voltage wires 112 which are shown running vertically across the upper metallization layer, electrically isolated from each other by dielectric 113. The power mesh 100 provides some inherent capacitance between overlapping voltage and ground wires. That is, wherever the Vdd wire of one metallization layer crosses the Vss wire of the other metallization layer a metal-to-metal capacitor is essentially effected. This capacitance however is not very significant due to the small area of intersection between the Vdd and Vss wires of adjacent metallization layers.
There is some additional coupling capacitance between adjacent Vss wires and Vdd wires on the same metallization layer, but again due to the relatively large distance between the two wires, this coupling capacitance is negligible. Typical application dimensions require an order of magnitude smaller wire spacing to provide substantial coupling capacitance.
Thus, as described above, conventional integrated circuit designs do not provide an adequate amount of well-distributed, high quality-factor coupling capacitance.